AMD Ramps 256-Core EPYC Venice on TSMC's 2nm Node
TL;DR
- Venice is the first HPC CPU in volume production on TSMC N2 GAA, a process node Intel has no server-class answer to through at least end of 2027.
- AMD's $5B equity stake in Anthropic makes a frontier AI lab a co-investor in AMD's GPU software stack, with Claude directly accelerating ROCm development.
- The 2GW MI450 GPU commitment in Helios racks bundles Venice CPUs, MI455X GPUs, and Pensando networking, mirroring Nvidia's bundled GB300 NVLink approach with a competing integrated stack.
The most quietly consequential number in AMD's Advancing AI 2026 keynote wasn't 256 or 70. It was 2. As in nanometers, and as in first. Tom's Hardware reports that AMD's sixth-generation EPYC, codenamed Venice, is the first high-performance computing product in the industry to reach production ramp on TSMC's N2 process, the node that transitions to nanosheet gate-all-around transistors.
Venice is a Zen 6 part. Peak configuration is 256 cores and 512 threads on the new SP7 socket, up from 192 cores and 384 threads on today's Turin generation. The platform pairs that with 16 memory channels for roughly 1.6 TB/s of aggregate memory bandwidth and PCIe 6.0, which is the piece that matters most for feeding AI accelerators. AMD's headline claim, as TechSpot summarizes, is more than a 70% improvement in overall performance and efficiency versus Turin, alongside more than a 30% increase in thread density.
Why this lands harder than the usual generational bump: hyperscaler capex is still being poured almost entirely into AI infrastructure, and the bottleneck at the rack level is thread density and CPU-to-GPU bandwidth, not clock speed. If Venice ships close to the specs AMD is quoting, the cost of hosting a given AI workload per rack drops meaningfully, and Intel's Xeon roadmap has to answer. AMD is coming off a Q2 where data center revenue more than doubled year-over-year, so Venice arrives into a segment that's already accelerating for them.
The keynote leaves the usual things unsaid. The 70% figure is vendor-stated against AMD's own prior-generation part, not independent silicon in a lab. AMD is ramping first in Taiwan, with TSMC's Arizona facility named as a future stop but no firm date given, so the near-term supply picture is Taiwan-concentrated. And the reporting doesn't give you a per-chip TDP, a price, or which hyperscaler has committed volume, all of which will decide whether Venice is a story about specs or a story about market share. The direction, though, is clear enough. If you sell x86 servers or design AI training racks, this is the number to watch.
What others are reporting
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AMD Investor Relations Read →
First-party source names follow-on chip 'Verano' for agentic AI, confirms TSMC Arizona production ramp, and cites SoIC-X and CoWoS-L advanced packaging across the portfolio.
Ramping 'Venice' on TSMC 2nm marks an important step toward accelerating next-generation AI infrastructure.
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GlobeNewswire via Manila Times Read →
AMD commits up to $5B equity in Anthropic and 2GW of MI450 GPUs in Helios racks starting H1 2027, with Claude accelerating ROCm as the software deliverable.
This collaboration brings together Anthropic's leadership in frontier AI with the full strength of AMD high-performance computing.
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TweakTown Read →
Focuses on supply chain mechanics: Taiwan production is live now, Arizona ramp follows, giving AMD the US-domestic sourcing option Intel currently lacks for its AI server lineup.
Venice is the first high-performance computing (HPC) product in the entire industry to enter volume production on TSMC's advanced 2nm process node.
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TechRadar Read →
The lone contrarian note: AMD's 'first on N2' claim holds in HPC but Apple's M-series may have shipped N2 silicon to consumers earlier, complicating the clean narrative.
Originally reported by tomshardware.com
Read the original article →Original headline: AMD Launches 256-Core EPYC Venice at Advancing AI 2026, First HPC CPU in Volume on TSMC 2nm With 70% Perf Jump