Intel CTO: Tool Supply Caps Wafer Capacity at 2x, Not 10x

Asked whether the chip industry has enough tools to double or 10x leading-edge wafer output, Intel CTO Pushkar Ranade told the Dwarkesh Podcast the uninflated answer: "Not 10X, but probably 2X, yes."

The constraint is equipment, not money. Ranade pointed at the chain of toolmakers and their sub-suppliers: "unless everybody produces more, you can't increase the output." He singled out lithography. ASML, he said, "produces fewer than 100" EUV machines a year, and the company does not plan to make significantly more "even by the end of the decade." Once a flow like Intel's 18A locks in a specific tool, "we can't just go and get a different tool for the same process."

Chris Auth, who leads development of the processes Intel is currently manufacturing, described the discipline on the engineering side. "What we've learned is that you don't want to do too much innovation in one node, because the more innovation that you do, the more complex it becomes," he said. 14A, the follow-on using High-NA EUV, is "in three years or two years from now."

Ranade also walked through Intel's work with Elon Musk's Terafab project. Musk, quoted in the episode, put the premise flat: "We either build the Terafab or we don't have the chips. And we need the chips, so we're going to build the Terafab." Ranade framed Intel's involvement as practical help rather than financing: "Unlike building a car, for example, this is such an intricate and complicated process that we thought we could work together to accelerate his bringing up his fab."

The podcast tour, published October 22, lands in a busy week for AI infrastructure coverage on who actually sets the pace of silicon.