OpenAI Pairs Jalapeño ASIC With AMD Turin, Skips Nvidia Vera

OpenAI's custom inference ASIC runs inside the lab paired with AMD, not Nvidia, as its host silicon. According to Tom's Hardware, the Jalapeño ASIC is deployed alongside AMD EPYC 'Turin' CPUs as hosts, with each host system carrying two Turin-class processors and 1.5TB of DRAM.

Richard Ho, VP and Head of Hardware at OpenAI, framed the Turin pick as a pragmatic de-risking call. On the obvious alternative, he said Nvidia's Vera standalone is 'a little bit behind… on that maturity level' at OpenAI's current scale.

The two-rack layout bundles 16 'Katsu' CPU trays and 16 'Vindaloo' accelerator trays holding 128 Jalapeño chips, stitched together by eight 'Chana' switch trays. OpenAI's figures put the paired system at roughly 160 kilowatts, split 31kW host and 130kW accelerator, and claim 1.5–1.9x more AI operations per watt and 1.7–3.6x lower end-to-end latency than baselines on GPT-OSS 120B and DeepSeek R1 670B. The design scales to 16 racks, up to 2,048 Jalapeño accelerators.

OpenAI partnered with Broadcom on silicon implementation and Celestica on system design. Jalapeño taped out in November 2025, with initial deployments planned for late 2026. It lands in a crowded quarter on our chips tracker, where 325 stories have crossed the desk in 90 days.