Qwenputer compiles a RISC-V CPU into Qwen3.5-4B weights

A 32-bit RISC-V CPU, compiled and inserted directly into a language model's weights. That is the pitch on the Hugging Face model card for Qwenputer, a Qwen3.5-4B variant published by Divyansh Agrawal.

The card describes the thing plainly: 'Qwenputer is an experimental model: Qwen3.5-4B with a 32-bit RISC-V CPU compiled and inserted directly into its weights. It is not a plugin, tool, or sandbox—the CPU consists of 11 transformer layers inserted before Qwen's own 32 layers with no learned weights.' The CPU uses Qwen's Gated DeltaNet state as RAM, where each row functions as a memory cell. It runs C and MicroPython inside the model's forward passes, and the author says it passes the official riscv-tests suites.

The arithmetic numbers are the headline. On greedy decoding across 40 problems per benchmark, Qwenputer lifts base Qwen3.5-4B from 55.0 to 97.5 on DeepMind's mul_big, from 72.5 to 97.5 on div_big, and from 75.0 to 97.5 on a synthetic integer arithmetic test. All numbers are self-reported on the model card.

Verification is where the card is most specific: '~230,000 output positions replayed through reference model showed zero mismatches.' KL divergence against the base model is given as 6e-4, with a noise floor of 5e-4. By weight count the computer is a small insertion, '~1M nonzero weights (mostly zero padding otherwise).'

The full model clocks about 3,200 trace tokens per second on an L4 GPU and ships at 9B parameters, 18.8 GB in bf16. Every benchmark the card reports is numeric. Two of the researchers we track flagged the release. The code and weights live at GitHub under MIT, with the Hugging Face checkpoint under Apache-2.0.