TSMC Pilots CoPoS Panel Packaging as CoWoS Sells Out to 2027

Packaging is the piece of the AI supply chain that hyperscalers most quietly worry about, and this week we got a clearer look at what TSMC thinks the fix is. The Information reported that the foundry is developing a new advanced packaging platform designed to challenge Intel's competing EMIB platform in the race to package ever-larger AI processors, as its current CoWoS lines sit fully booked through 2027.

The platform, called CoPoS, or Chip-on-Panel-on-Substrate, swaps traditional round 12-inch wafers for 310×310mm rectangular panels, which tile larger AI dies more efficiently and cut unused edge area. Pilot production reportedly commenced around June 2026 at VisEra's Longtan plant in Taiwan, running a dual-track evaluation with one line led by major global equipment vendors and another adopting solutions from Taiwanese equipment makers. Mass production is not expected until the second half of 2028 or possibly into 2029.

The timing matters because CoWoS capacity is fully booked through 2027, with flagship AI players such as Nvidia, AMD and Google holding the bookings. That has pushed second-tier ASIC vendors and major U.S. chipmakers to start exploring Intel's EMIB and Foveros as alternative back-end options, which gives Intel Foundry perhaps its clearest opening in years while TSMC's replacement platform is still on the pilot line.

TSMC is also working with Innolux and Ibiden to evaluate glass substrates for CoPoS. Reported simulation results show glass improving packaging warpage by 16%, reducing effective coefficient of thermal expansion by 19% and cutting inductance by 42% on power integrity, but commercial-scale glass output is not expected until after 2030. Take the pilot dates and simulation figures as reported, not settled. What the reporting does not give you is the per-package cost versus CoWoS, which customers have actually committed to CoPoS reticles, or how the pilot line is yielding. The honest read is that AI packaging stays the binding constraint for roughly two more years, and any accelerator roadmap through 2027 has to plan around that ceiling.