IBM's 0.7nm NanoStack Claims 50% Performance Gain Over 2nm
TL;DR
- IBM Research projects NanoStack-class chips at 9,000 TOPS versus today's 1,500 TOPS, with IBM estimating LLM training timelines could fall from three months to two weeks.
- The '0.7 nanometer' label is a marketing convention with no direct physical correspondence to transistor gate dimensions, per MIT Technology Review.
- Sequential 3D stacking requires processing above 900 degrees Celsius while bonded lower layers can safely sustain only around 400 degrees Celsius, the thermal gap independent researchers identify as the primary production barrier.
The chip industry has been telling investors and governments for years that the laws of physics are running out of room. IBM's announcement of a 0.7 nanometer architecture, described in detail on IBM's research newsroom, suggests there is at least a decade more road ahead.
The core claim is architectural, not just a size number. IBM calls the design "nanostack," a 3D nanosheet approach that vertically stacks and staggers transistors, allowing different materials to be used in each layer for independent performance and efficiency tuning. The result, IBM says, is a fingernail-sized chip carrying nearly 100 billion transistors, roughly double the density of its 2021-era 2nm design, with up to 50% performance improvement and 70% greater energy efficiency over that baseline.
"With our new nanostack architecture, we're not just making smaller transistors, we're reinventing how chips are built," said Jay Gambetta, IBM Research Director and IBM Fellow. The company is backing the research with physical infrastructure: its Albany, New York facility will house High NA EUV lithography equipment from ASML, developed collaboratively with Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions.
The honest caveat is that IBM's semiconductor research announcements and their manufacturing reality operate on very different timelines. IBM's own projection here is "within 5 years" for production feasibility, a number to hold loosely, and the announcement does not name a major foundry manufacturing partner. IBM's research division does not run a consumer fab, so the path from Albany lab result to production silicon involves parties not yet identified.
For teams building AI infrastructure, the 50% performance and 70% energy efficiency claims are the numbers worth tracking, alongside which foundry eventually commits to the nanostack architecture. IBM estimates at least a decade of continued scaling potential with this approach, which matters more for long-term chip roadmap planning than the headline node number.
What others are reporting
-
MIT Technology Review Read →
Independent expert challenge: yield and thermal concerns from U of Illinois professor Qing Cao; Hutcheson's 10-15-year Moore's Law runway estimate; junctionless transistors cited as a competing research path.
"This puts another 10, 15 years on the roadmap." - Dan Hutcheson, TechInsights
-
IBM Research Read →
IBM's research blog carries the 9,000 TOPS projection and LLM training estimate absent from the newsroom release, plus technical depth on wafer bonding and independent NFET/PFET channel optimization.
"In a 7 angstrom chip the size of a fingernail, there are roughly 100 billion transistors."
-
Seeking Alpha Read →
Market reaction angle: IBM shares up roughly 5% in premarket trading, with the five-year production estimate shaping investor expectations on commercialization timing.
Shared on Bluesky by 1 AI expert
Originally reported by ibm.com
Read the original article →Original headline: IBM Debuts World's First Sub-1 Nanometer Chip — 0.7nm NanoStack Architecture Packs 100 Billion Transistors, Claims 50% Performance Gain and 70% Energy Efficiency Improvement Over 2nm