IBM's 0.7nm NanoStack Claims 50% Performance Gain Over 2nm
TL;DR
- IBM's 0.7nm NanoStack architecture packs nearly 100 billion transistors on a fingernail-sized chip, double the density of its 2nm design.
- The design claims up to 50% performance improvement and 70% greater energy efficiency compared to IBM's 2nm chip.
- IBM projects production feasibility within five years and estimates at least a decade of continued scaling potential.
The chip industry has been telling investors and governments for years that the laws of physics are running out of room. IBM's announcement of a 0.7 nanometer architecture, described in detail on IBM's research newsroom, suggests there is at least a decade more road ahead.
The core claim is architectural, not just a size number. IBM calls the design "nanostack," a 3D nanosheet approach that vertically stacks and staggers transistors, allowing different materials to be used in each layer for independent performance and efficiency tuning. The result, IBM says, is a fingernail-sized chip carrying nearly 100 billion transistors, roughly double the density of its 2021-era 2nm design, with up to 50% performance improvement and 70% greater energy efficiency over that baseline.
"With our new nanostack architecture, we're not just making smaller transistors, we're reinventing how chips are built," said Jay Gambetta, IBM Research Director and IBM Fellow. The company is backing the research with physical infrastructure: its Albany, New York facility will house High NA EUV lithography equipment from ASML, developed collaboratively with Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions.
The honest caveat is that IBM's semiconductor research announcements and their manufacturing reality operate on very different timelines. IBM's own projection here is "within 5 years" for production feasibility, a number to hold loosely, and the announcement does not name a major foundry manufacturing partner. IBM's research division does not run a consumer fab, so the path from Albany lab result to production silicon involves parties not yet identified.
For teams building AI infrastructure, the 50% performance and 70% energy efficiency claims are the numbers worth tracking, alongside which foundry eventually commits to the nanostack architecture. IBM estimates at least a decade of continued scaling potential with this approach, which matters more for long-term chip roadmap planning than the headline node number.
Originally reported by ibm.com
Read the original article →Original headline: IBM Debuts World's First Sub-1 Nanometer Chip — 0.7nm NanoStack Architecture Packs 100 Billion Transistors, Claims 50% Performance Gain and 70% Energy Efficiency Improvement Over 2nm