Imec 3D CCD memory targets AI memory wall
Key insights
- Imec's 3D CCD prototype achieves charge-transfer above 4 MHz using IGZO instead of silicon, targeting DRAM-like access speeds.
- The architecture could theoretically scale beyond 200 stacked layers, matching commercial NAND density roadmaps.
- Imec positions the design as a lower-cost, higher-endurance alternative to HBM for AI memory bandwidth demands.
Why this matters
AI training and inference workloads are increasingly bottlenecked by memory bandwidth and cost, with HBM prices constraining which companies can afford frontier-scale compute; a manufacturable hybrid that matches NAND density at near-DRAM speeds would reshape that cost curve significantly. The use of IGZO instead of silicon opens a materials pathway that existing NAND fabs could potentially adapt, which matters for anyone modeling the capital expenditure side of AI infrastructure over the next five years. Imec's institutional role as a neutral research hub means this prototype will be licensed or co-developed with major memory makers rather than commercialized in-house, so Samsung, Micron, and SK Hynix are the immediate stakeholders to watch for follow-on announcements.
Summary
Imec, the Belgian semiconductor research institute, has demonstrated the first 3D implementation of charge-coupled device memory, reviving a technology once confined to camera sensors to attack one of AI's most stubborn infrastructure bottlenecks.
Presented at IEEE's International Memory Workshop on May 12, the prototype uses indium gallium zinc oxide (IGZO) instead of conventional silicon, enabling charge-transfer speeds above 4 MHz. The design stacks memory vertically the way commercial NAND flash does, with imec claiming it could in principle exceed 200 stacked layers while delivering access speeds closer to DRAM than to NAND.
Essentially: (imec) is proposing a third memory class that borrows density from NAND and speed from DRAM, targeting the gap that currently forces AI systems to pay a steep premium for high-bandwidth memory like HBM.
- Charge-transfer above 4 MHz puts the prototype meaningfully faster than NAND read latencies without requiring DRAM's charge-leakage refresh cycles.
- IGZO as the channel material is a deliberate choice: it has lower leakage current than silicon, which is why imec claims improved endurance over existing flash.
- The 200-layer scalability claim mirrors where leading NAND vendors (Samsung, Micron, SK Hynix) are today, suggesting a plausible manufacturing path.
Whether IGZO-based CCD memory reaches volume production is still years away, but the IEEE presentation marks the first 3D silicon-free CCD prototype, which is a meaningful proof-of-concept milestone for the memory industry.
Potential risks and opportunities
Risks
- HBM incumbents (SK Hynix, Samsung) could slow-walk licensing discussions to protect existing HBM revenue streams, delaying any commercial availability past the 2028-2030 window when AI memory demand peaks.
- IGZO supply chains are currently tuned for display panels (Sharp, Japan Display) rather than memory volume, creating a materials bottleneck that could inflate per-wafer costs if demand scales faster than supply.
- If imec's endurance and scalability claims do not replicate in third-party process nodes, AI hardware vendors (Nvidia, AMD, Google TPU teams) that factor the technology into next-generation memory roadmaps face a planning gap with no near-term substitute.
Opportunities
- IGZO materials suppliers and deposition equipment vendors (Applied Materials, Tokyo Electron) are positioned to capture early development contracts as memory fabs begin process qualification work.
- Cloud providers (Microsoft Azure, Google Cloud, AWS) with long AI infrastructure capex cycles could use imec's roadmap to negotiate lower HBM forward contracts, leveraging the credible competitive threat.
- Fabless AI chip startups designing memory-centric architectures (Groq, Cerebras, SambaNova) have a window to co-design accelerators around the CCD memory interface spec before the large incumbent chipmakers lock in preferred-partner agreements with imec.
What we don't know yet
- Which commercial memory manufacturers (Samsung, Micron, SK Hynix) have active co-development agreements with imec on this specific CCD architecture as of May 2026.
- Whether the 4 MHz charge-transfer speed holds at scale across 200-layer stacks or was measured only on shallow prototype configurations.
- Timeline to a process-design kit or pilot-line tape-out that would let foundry partners assess yield and cost-per-bit against current HBM3E.
Originally reported by TechRadar
Read the original article →Original headline: Imec Demonstrates First 3D CCD Memory Combining NAND Density With DRAM-Like Access — Claims Breakthrough Past AI Memory Wall