Qing Cao silicon stack extends Moore's Law timeline
Key insights
- Qing Cao's team demonstrated three-layer silicon stacks with high yield at wafer scale, backed by IBM, Intel, and TSMC through the NSF ASAP center.
- Monolithic 3D silicon integration bonds layers during fabrication itself, unlike chiplet packaging which assembles separate dies post-manufacture.
- The team is transferring the process to a commercial foundry, meaning the technology may reach production within years rather than decades.
Why this matters
AI hardware is increasingly the bottleneck for model training and inference, and monolithic 3D silicon integration directly addresses the density ceiling that horizontal lithography scaling has been approaching for years. IBM, Intel, and TSMC backing the NSF ASAP center's commercialization path signals this is not academic: advanced packaging alternatives may lose ground to in-fabrication vertical stacking as a preferred density strategy within the decade. For AI infrastructure planners and chip procurement teams, the key question is whether next-generation accelerator roadmaps currently built around chiplet and 2.5D interposer architectures will need revision as monolithic 3D becomes foundry-ready.
Summary
University of Illinois engineers have demonstrated a way to stack silicon transistor layers directly during fabrication, a density breakthrough backed by IBM, Intel, and TSMC.
Led by Qing Cao through the NSF ASAP center, the work achieves monolithic 3D integration at wafer scale. Unlike chiplet packaging, which assembles dies post-manufacture, this bonds layers sequentially during fabrication, compounding density vertically without shrinking transistors further.
Essentially: (IBM, Intel, TSMC) are funding the path to commercialization.
- Three-layer stacks delivered high yield and low variability at wafer scale
- Foundry transfer is in active preparation
- Vertical stacking sidesteps current lithography limits
This moves vertical silicon integration from research demonstration to a plausible foundry process.
Potential risks and opportunities
Risks
- If thermal dissipation in stacked layers proves unmanageable at commercial density, IBM and Intel may redirect investment back to chiplet packaging, delaying any foundry transfer past 2030
- TSMC could absorb the process internally under its own IP framework, potentially locking smaller foundries (GlobalFoundries, Samsung Foundry) out of licensing the NSF-funded technique
- High process complexity in sequential layer bonding could suppress yield enough in volume production to make the economics worse than advanced node shrinks, undermining the Moore's Law extension case
Opportunities
- EDA vendors (Synopsys, Cadence) can build 3D-native design tools targeting the NSF ASAP process flow ahead of commercial foundry transfer, locking in early toolchain advantage
- AI chip startups (Groq, Cerebras, Tenstorrent) have a near-term opening to engage the ASAP center as design partners before the process is locked into IBM, Intel, and TSMC workflows
- Advanced packaging materials suppliers (Entegris, DuPont) that qualify materials for wafer-level sequential layer bonding stand to capture share as the process moves toward commercial volume
What we don't know yet
- Timeline to commercial foundry transfer: the team says they are preparing but no specific milestone or target year was disclosed
- Whether the demonstrated three-layer yield numbers meet the thresholds IBM, Intel, and TSMC require for high-volume production qualification
- Thermal management at scale: stacking transistor layers compounds heat density and the source does not address how the method handles that at commercial volumes
Originally reported by sciencedaily.com
Read the original article →Original headline: New 3D Silicon Chip Breakthrough Could Extend Moore's Law for Years