Samsung Shows HBM5 Mockup at Computex, 2028 Target
Key insights
- Samsung's HBM5 base dies will be built on its in-house 2nm foundry process, with mass production targeted around 2028.
- HBM5 ships in 12-, 16-, and 20-layer DRAM stack variants, with a follow-on HBM5E generation using a 1d DRAM node already in development.
- Both Samsung HPB and SK hynix iHBM target the D2D PHY thermal bottleneck, making thermal architecture the defining HBM engineering challenge.
Why this matters
HBM5 sets the memory bandwidth ceiling for AI accelerators from roughly 2028 onward, making Samsung's thermal architecture choices binding constraints on GPU and custom ASIC designs being planned today. The reliance on Samsung's in-house 2nm foundry process ties next-generation AI memory supply to that process node's maturity, adding a new supply concentration risk to the AI hardware stack. Samsung's public disclosure of HPB competing directly with SK hynix's iHBM signals that thermal management has replaced layer count as the primary differentiation battleground in high-bandwidth memory.
Summary
Samsung put its 8th-generation HBM5 memory on display at Computex 2026 in Taipei on June 2, marking the first public mock-up ahead of a mass production target around 2028.
Base dies use Samsung's in-house 2nm foundry process, with 12-, 16-, and 20-layer stack options. A follow-on 1d DRAM node is already in development for a future HBM5E generation.
Essentially: (Samsung, SK hynix) are racing to solve HBM5 thermal limits before production launches.
- Samsung's Heat Path Block (HPB) creates an independent thermal path inside the D2D PHY region, the primary heat source between HBM and GPUs, already validated in HBM4E
- Samsung Electronics DS CTO Song Jae-hyuk confirmed HPB reliability and stability are fully verified
- SK hynix's competing iHBM integrates cooling elements directly into the HBM package for the same generation
The 2028 target hinges on proving HPB holds at 16- and 20-layer scale, not just stacking more DRAM.
Potential risks and opportunities
Risks
- Samsung's 2nm foundry process is unproven at HBM base-die scale; yield shortfalls could push mass production past 2028, delaying AI hardware programs dependent on HBM5
- SK hynix's iHBM competing thermal architecture could reach customer qualification faster, pressuring Samsung's premium HBM market share at a critical technology transition
- If HPB thermal validation at 16- and 20-layer HBM5 stack heights surfaces issues beyond what was tested in HBM4E, reliability concerns could affect adoption of Samsung's entire 2nm-based memory roadmap
Opportunities
- Samsung Foundry gains a strategic anchor customer in its own memory division for the 2nm node, strengthening its process capacity narrative before external AI chip customers commit volume
- Advanced packaging and thermal interface material suppliers benefit from HPB-style designs requiring new materials at D2D PHY interfaces across both Samsung and SK hynix next-generation HBM programs
- AI hardware designers can begin HBM5E architecture planning now that Samsung has disclosed its 1d DRAM process path, giving early co-development partners a visibility advantage into post-2028 memory infrastructure
What we don't know yet
- No customer qualification timelines, shipment volumes, or pricing disclosed for HBM5 or the follow-on HBM5E generation
- Whether SK hynix's iHBM solution will reach production readiness before or after Samsung's approximately 2028 HBM5 target
- Which AI accelerator designers are co-developing with Samsung's HBM5 program and will anchor early production volumes
Originally reported by trendforce.com
Read the original article →Original headline: Samsung Unveils First-Ever HBM5 Mockup at Computex, Production Targeted Around 2028