TSMC's Taiwan Packaging Grip Creates AI's Next Supply Chokepoint
TL;DR
- TSMC sends 100% of chips to Taiwan for advanced packaging, including those made at its Phoenix, Arizona fabrication plant.
- TSMC's CEO stated CoWoS packaging capacity is sold out through 2026; Google reportedly cut its TPU production target by roughly 25%.
- US advanced packaging facilities at TSMC's Arizona sites won't reach full volume production until later this decade.
The chip story most people have been following is about wafer fabs: where silicon is etched, whether TSMC builds in Arizona, whether CHIPS Act funding moves the needle. The New York Times published a piece this week that shifts the frame to what happens after the wafer, and it is a harder problem.
The step at issue is advanced packaging, specifically the CoWoS (Chip on Wafer on Substrate) process that binds memory, logic, and interconnects into a finished AI processor. TSMC operates the world's most advanced packaging facilities almost exclusively in Taiwan. The immediate consequence is stark: TSMC currently sends 100% of its chips to Taiwan for this packaging step, including chips already manufactured at its Phoenix, Arizona fab. AI hardware built on US soil still requires what one analysis calls "a 12,000-mile round trip to Taiwan for final assembly." Nvidia has secured most of TSMC's available CoWoS capacity, and cloud providers report lead times for GPU clusters stretching 12 to 18 months.
The capacity crunch has real production consequences. C.C. Wei, TSMC's CEO, has said CoWoS is sold out through 2026. Google reportedly cut its 2026 TPU production target by around 25%, from roughly 4 million to 3 million units, because of CoWoS constraints. TSMC plans to roughly double CoWoS capacity over the next two years, but the starting point is tight enough that expansion does not erase the bottleneck in the near term.
US policy is moving but slowly. TSMC's Arizona expansion includes advanced packaging facilities alongside wafer fabs, and the company has a partnership with Amkor Technology for a Peoria, Arizona site. Those operations are not expected to reach full volume production until later this decade. A new packaging facility that Advanced Semiconductor Engineering and WUS Printed Circuit Co. plan in Kaohsiung, Taiwan is slated for completion by September 2029, which adds capacity without reducing geographic concentration.
The open question the reporting does not fully resolve is how quickly Intel's alternative packaging approaches, Foveros for 3D stacking and EMIB for chiplet interconnection, could reach the scale needed for AI accelerators. Until that answer emerges, the Arizona buildout timeline is the thing to watch for anyone assessing whether the US can close this gap before the Taiwan dependency is tested by something it cannot route around.
Originally reported by nytimes.com
Read the original article →Original headline: NYT Deep Dive: Advanced Chip Packaging Is Now Almost Entirely Reliant on TSMC's Taiwan Operations — US Efforts to Build Domestic Capacity Face Steep Technical and Geopolitical Hurdles