Meta's Vistara CXL chip recycles DDR4 into DDR5-only AI servers

Memory is quietly becoming the bottleneck the AI hyperscalers do not want to talk about, and Meta has just disclosed a fairly surgical answer to it. According to Tom's Hardware, the company has built a custom CXL 2.0 ASIC called Vistara that bolts legacy DDR4 DIMMs onto brand-new servers that physically only support DDR5, then exposes the older memory to Linux as a separate NUMA tier.

The hardware lives inside what Meta calls a MemServer, and as detailed by The Register, each box pairs 768 GB of local DDR5-6400 with 256 GB of CXL-attached DDR4-2400 for a total of around 1 TB. Bandwidth on the DDR4 tier lands at roughly 76 GB/s against 614 GB/s on the local DDR5, with the kernel migrating cold pages out to the slower side. The ASIC itself talks PCIe Gen5 x16 to the host and drives two independent 72-bit DDR4 channels with up to 256 GB per chip, attached to servers running AMD EPYC 'Turin' processors.

The numbers Meta is putting on the result are the part to take seriously, with the caveat that they come from Meta's own paper and have not been independently benchmarked. The company reports the architecture cuts the number of AI inference servers it needs by up to 25 percent, and that by mitigating out-of-memory events the CXL tier reduces job-restart and resource-fragmentation overhead by 33 percent. The motivation is more embarrassing than glamorous: Meta says it can't expand memory in around 40 percent of its fleet, even though DIMMs are useful for seven to ten years against a three-to-five year server lifespan.

The honest caveat is that this is a paper being presented at ISCA 2026 rather than a publicly available product, and the reporting does not give you fleet-wide deployment counts, failure rates on the recycled DIMMs at scale, or how Meta intends to handle DDR4's eventual exit from the supply chain. Nor is it clear whether Vistara will land in the Open Compute Project, which is what would let smaller operators copy the trick.

For everyone else watching the DRAM squeeze, the strategic read is uncomfortable. Hyperscalers with their own silicon teams can simply build around the shortage, while everyone else pays the spot price. CXL controller vendors now have a very loud reference customer to point at, and the AMD EPYC Turin platform has gained a real memory-expansion story that previously lived only in slide decks.